1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and manufacturing method thereof and, more particularly, to a structure of a memory cell transistor in a non-volatile semiconductor memory device and manufacturing method thereof.
2. Description of the Background Art
Conventionally, a DiNOR (Divided bit line NOR) type flash memory is known as a non-volatile semiconductor memory device.
FIGS. 12 and 13 show an example of a manufacturing method for a memory cell transistor in a conventional DINOR type flash memory.
As shown in FIG. 12, a multilayered structure of a gate isolation film 5, a first polysilicon film 2a, an isolation film 6, a second polysilicon film 2b, a silicide film 2c and an isolation film 7 is formed on the main surface of a semiconductor substrate 1.
Next, a resist 8 is formed so as to cover regions where source regions of memory cell transistors are formed and to expose regions where drain regions are formed. Using this resist 8 as a mask, P and As are, respectively, implanted into the main surface of the semiconductor substrate 1. Thereby, drain regions 12 which have nxe2x88x92 impurity regions 12a and n+ impurity regions 12b are formed.
Next, as shown in FIG. 13, a resist 8 is formed so as to cover the drain regions 12 of the memory cell transistors and to expose the regions where the source regions are formed. Using this resist 8 as a mask, As and B are, respectively, implanted into the main surface of the semiconductor substrate 1. Thereby, source regions 11 which have pxe2x88x92 impurity regions 11a and n+ impurity regions 11b are formed.
A conventional DINOR type flash memory which has the above described structure carries out writing by utilizing the FN tunnel phenomenon so as to draw out electrons from the FG to the drain region 12 and carries out erasing by utilizing the FN tunnel phenomenon so as to inject electrons from the entire surface of the channel region into the FG. Therefore, though high speed erasing is possible, writing is slow (approximately 1 ms), which raises the problem of making a byte program difficult.
Then, the present invention is provided in order to solve the above described problem. The purpose of the present invention is to provide a non-volatile semiconductor memory device which can carry out both the writing operation and the erasing operation at high speed.
According to one aspect of the present invention, a non-volatile semiconductor memory device is provided with a semiconductor substrate having a main surface, source and drain regions of memory cell transistors formed on the surface, and gates of the memory cell transistors which are formed on the main surface via a gate isolation film and which are located between the source and the drain regions. Then, the source regions include first high impurity concentration regions of a first conductive type and first low impurity concentration regions of a second conductive type while the drain regions include second high impurity concentration regions of a first conductive type and second low impurity concentration regions of a second conductive type.
The present inventors have endeavored to gain a non-volatile semiconductor memory device which can carry out both the writing and the erasing operations at high speed and have devised a combination of channel hot electron (hereinafter referred to as xe2x80x9cCHExe2x80x9d ) writing and erasing on the entire surface of the channel. That is to say, writing is carried out by injecting CHEs into the FG and erasing is carried out by utilizing the FN tunnel phenomenon on the entire surface of the channel so as to draw out electrons from the FG. In this way, by adopting the CHE writing, high speed byte writing can be carried out while, by carrying out the erasing which utilizes the FN tunnel phenomenon on the entire surface of the channel (hereinafter referred to xe2x80x9cerasing on the entire surface of the channelxe2x80x9d ), the erasing operation can be carried out at high speed. Therefore, the present inventors have further endeavored to gain a memory cell transistor structure which can be adopted in a related non-volatile semiconductor memory device and also have devised the above described structure. This structure is provided with the drain regions having the second high impurity concentration regions of the first conductive type and the second low impurity concentration regions of the second conductive type and, thereby, it is possible to make CHEs occur in the vicinity of the drain regions so as to enable the effective carrying out of the CHE writing. In addition, at the time of erasing, the erasing on the entire surface of the channel can be carried out by applying a predetermined voltage to the gates, to the source regions of the memory cell transistors and to the substrate.
It is preferable that the impurity concentration of the first conductive type included in the first high impurity concentration regions be higher than the impurity concentration of the first conductive type included in the second high impurity concentration regions and the impurity concentration of the second conductive type included in the first low impurity concentration regions is the same as, or is higher than, the impurity concentration of the second conductive type included in the second low impurity concentration regions.
Thereby, as shown in FIG. 9, for example, the junction withstand voltage (BVds) between the source region and the drain region can be maintained even in the case that the gate length is made shorter. At this time the resistance of the source region can also be maintained at a low level. In addition, by properly adjusting the impurity concentration of the second conductive type, the threshold voltage (UV-Vth) under the initial condition of the memory cell transistor can be set at a desired value.
It is preferable that the first high impurity concentration regions be formed within the first low impurity concentration regions while the second high impurity concentration regions be formed within the second low impurity concentration regions.
In this way, by surrounding the high impurity concentration regions with the low impurity concentration regions, the junction withstand voltage between the source regions and the drain regions can be maintained.
It is preferable that the impurity concentration of the first conductive type included in the first high impurity concentration regions be two or more times as high as the impurity concentration of the first conductive type included in the second high impurity concentration regions while the impurity concentration of the second conductive type included in the first low impurity concentration regions is two or more times as high as the impurity concentration of the second conductive type included in the second low impurity concentration regions. Thereby, the above described effects become more evident.
The impurity concentration of the first conductive type included in the first high impurity concentration regions is two or more times as high as the impurity concentration of the first conductive type included in the second high impurity concentration regions while the impurity concentration of the second conductive type included in the first low impurity concentration regions is equal to the impurity concentration of the second conductive type included in the second low impurity concentration regions. In this case also, the above described effects become more evident.
The impurity of the first conductive type is an n type impurity while the impurity of the second conductive type is a p type impurity. The gate length of the memory cell transistors is 0.2 xcexcm or less. In this case, the present invention becomes especially useful.
According to another aspect of the present invention, a non-volatile semiconductor memory device is provided with a semiconductor substrate having a main surface, source regions and drain regions of memory cell transistors formed on the main surface, and gates of the memory cell transistors which are formed on the main surface via a gate isolation film and which are located between the source regions and the drain regions. The source regions are formed by the impurity regions of the first conductive type while the drain regions include high impurity concentration regions of the first conductive type and low impurity concentration regions of the second conductive type.
In the case according to this aspect, the CHE writing and erasing on the entire surface of the channel can also be carried out in the same way as in the case according to the above previously described aspect.
It is preferable that the impurity concentration of the first conductive type included in the above described impurity regions be higher than the impurity concentration of the first conductive type included in the high impurity concentration regions. Thereby, the resistance of the source regions can be lowered effectively.
It is preferable that the second high impurity concentration regions be formed within the low impurity concentration regions. Thereby, as shown, for example, in FIG. 11, the BVds can be maintained even in the case that the gate length of the memory cell transistors are made shorter. Also the UV-Vth can be set low.
It is preferable that the impurity concentration of the first conductive type included in the first high impurity concentration regions be two or more times as high as the impurity concentration of the first conductive type included in the second high impurity concentration regions. Thereby, the above described effects become more evident.
It is preferable that the impurity of the first conductive type be an n type impurity while the impurity of the second conductive type is a p type impurity. It is also preferable that the gate length of the memory cell transistors be 0.2 xcexcm or less. In this case, the present invention is especially useful.
According to one aspect of the present invention, a manufacturing method for a non-volatile semiconductor memory device comprises the following steps of: formation of gates of the memory cell transistors on the main surface of a semiconductor substrate via a gate isolation film; formation of source regions and drain regions of the memory cell transistors having high impurity concentration regions of the first conductive type within low impurity concentration regions of the second conductive type by implanting an impurity of the first conductive type and an impurity of the second conductive type into the main surface by using the gates as a mask; formation of a mask film so as to cover the drain regions and to expose the source regions; and implantation of an impurity of the first conductive type into the high impurity concentration regions of the source regions using the mask film.
By implanting the impurity of the first conductive type and the impurity of the second conductive type into the semiconductor substrate under predetermined conditions by using the gates of the memory cell transistors as a mask as described above, the source regions and the drain regions can be formed by low impurity concentration regions and high impurity concentration regions of different conductive types. In addition, since the impurity of the first conductive type is implanted into the regions where the source regions are formed by using the mask covering the regions where the drain regions are formed, the concentration of the high impurity concentration of the first conductive type can further be enhanced in the source regions. Since the memory cell transistors have such a source and drain region structure the CHE writing and the erasing on the entire source of the channel can be carried out as described above.
It is preferable that the manufacturing method be provided with the step of implantation of an impurity of the second conductive type into the low impurity concentration regions of the source regions by using the above described mask film. Thereby, the UV-Vth of the memory cell transistors can be set at a desired value.
According to another aspect of the present invention, a manufacturing method for a non-volatile semiconductor memory device is provided with the following steps of: formation of gates of memory cell transistors on the main surface of a semiconductor substrate via a gate isolation film; formation of source regions of the memory cell transistors and high impurity concentration regions in drain regions of the memory cell transistors by implanting an impurity of the first conductive type into the main surface using the gates as a mask; formation of low impurity concentration regions surrounding the high impurity concentration regions by implanting an impurity of the second conductive type into the drain regions using the gates as a mask; formation of a mask film so as to cover the drain regions and to expose the source regions; and implantation of an impurity of the first conductive type into the source regions by using the mask film. Here, the high impurity concentration regions in the drain regions may be formed after forming the low impurity concentration regions.
In the present aspect also, the memory cell transistors which can carry out the CHE writing and the erasing on the entire surface of the channel can be gained since the drain regions can be formed by impurity regions of different conductive types.
A plurality of memory cell transistors are formed on the main surface and an isolation film is formed on the gates. Here, when the gap between the gates on the side of source regions is denoted as x and the height from the main surface to the top surface of the isolation film is denoted as y, the implantation angle xcex8 of the impurity of the second conductive type is made to be a value larger than tanxe2x88x921(x/y).
By controlling the implantation angle xcex8 of the impurity of the second conductive type in the above described way, the implantation of the impurity of the second conductive type into the source regions through the gates, the isolation films or the like, of the memory cell transistors can be prevented. Thereby, the impurity of the second conductive type can be implanted solely into the drain regions.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.